1. Field of the Invention
The present invention concerns PCM type interfaces (where PCM stands for “Pulse Code Modulation”).
2. Description of the Related Art
PCM is a method for synchronous multiplexing and encoding, in which audio signals are represented in the form of a digital data signal multiplexed by time division multiple access (TDMA). A PCM signal is therefore a digital signal obtained by temporal multiplexing of multiple analog voice signals sampled using the same reference for sampling.
As is shown in FIG. 1, a prior art PCM interface of a functional unit 10 comprises:                a first clock terminal Clk and a second clock terminal FS, each configured to receive or to send a bit-level synchronizing clock signal CLK_Bit and a frame-level synchronizing clock signal CLK_Frame; and,        a data input terminal IN and a data output terminal OUT, respectively configured to receive a data signal PCM_Rx and to send a data signal PCM_Tx in duplex mode.        
In telephony applications, the audio spectrum considered as significant corresponds to a band of 300-3400 Hz. As it is known that the sampling frequency must be more than twice the maximum frequency of this band (Shannon's theorem), the value of the sampling frequency chosen is typically 8 kHz. Therefore the time between two successive samples from an audio channel (also called audio path) is equal to 125 μs. The frequency of the frame-level synchronizing clock signal CLK_Frame is equal to the audio signal sampling frequency. In this manner, there is a sample of a given audio channel per frame.
If an audio signal sample is encoded into 8 bits, at 64 kilobits/channel, the frequency of the bit-level synchronizing clock signal CLK_Bit is then equal to N×64 kHz, where N is the number of channels multiplexed by TDMA within a frame, meaning within a period of the frame-level synchronizing clock signal CLK_Frame. The fraction of a frame allocated to a given channel is called the time interval (TI). In the European system standardized by the CCITT (recommendation G732), N is equal to 32 (known as “32 channel PCM”), such that the frequency of the CLK_Bit signal is equal to 2.048 MHz. Therefore for each frame there are 30 voice channels (TI numbers 1 to 15 and 17 to 30), 1 signaling channel (TI number 16) for transmitting the signaling in flag mode or in channel by channel mode, and a synchronization channel (TI number 0) for transmitting frame synchronization information.
The high availability and low cost of various PCM interface circuits is such that almost all audio systems appearing over the last few decades use PCM, although there is a current tendency to prefer the format of the I2S (Inter-IC Sound) standard, which allows the stereo transmission of audio data (in particular music).
In standard PCM interfaces, generally the clock terminals Clk and FS are bi-directional/reversible, such that the unit 10 delivers the respective clock signals CLK_Bit and CLK_Frame, or receives them from the outside, via these two terminals. In the first case, unit 10 is said to be a master unit. In the second case, unit 10 is said to be a slave unit. The type, master or slave, of the functional units of a system may thus be configured as needed for the application.
At a given moment the unit 10 may receive a data signal PCM_Rx via the IN terminal, and send a data signal PCM_Tx via the OUT terminal. The communication of data therefore occurs in duplex mode. The function of the IN and OUT terminals is fixed, however.
As is shown in FIG. 2, an electronic system comprises for example several functional units 11 to 14 which communicate with each other using the PCM, and each has a standard PCM interface. The PCM interfaces are connected by a connecting network 20 which is fixed, meaning not configurable during operation. Such a connecting network comprises point-to-multipoint links. Only one of the functional units is a master, with its clock inputs Clk and FS respectively configured to send the clock signal CLK_Bit and the clock signal CLK_Frame. The others are slave units, with their clock inputs Clk and FS respectively configured to receive the clock signal CLK_Bit and the clock signal CLK_Frame.
In the example represented in FIG. 2, the unit 12, which may for example be the master unit, can send data to each of the units 11, 13, and 14 (its OUT output is connected to the IN input of each of these three units). Similarly, it can receive data from each of these three units (its IN input is connected to the OUT output of each of these three units).
On the other hand, the functional units 11, 13 and 14 cannot directly exchange data with each other without generating a transmission conflict (their respective IN inputs connected together, and their respective OUT outputs connected together). In practice, when unit 11 wants to exchange data with unit 13, for example, these two units communicate indirectly through unit 12.
This generates transmission delays, requires the providing of additional resources in functional unit 12 (particularly buffers), and necessitates more complex means of control in order to operate the system under the different possible utilization scenarios.